Review of
Instruction Fetch
We
have discussed the common fetch sequence in previous lectures.
We
have given both the sequence of microoperations and the corresponding sequence
of control signals.?Remember that memory
timings restrict access to memory during the
(Fetch, T1) time slot, so we elect to update the Program Counter during this
time.
Fetch,
T0:牋牋牋 (PC) ?/span> B1, tra1,
B3 ?/span> MAR, READ.
Fetch,
T1:牋牋牋 (PC) ?/span> B1, 1 ?/span> B2, add,
B3 ?/span> PC.
Fetch,
T2:牋牋牋 (MBR) ?/span> B2, tra2,
B3 ?/span> IR.
This lecture focuses on the
impact of incrementing the program counter on
牋牋牋?1)牋牋 the design of the ALU, and
牋牋牋?2)牋牋 the bus structure of the CPU.
It
is immediately obvious that the ALU must have either an addition operation or
an increment (add 1) operation.?For
simplicity, the design uses a simple addition operation, associated with the
control signal 揳dd?/b>.
We
have always assumed that the CPU has three internal data busses.
We now show why such a
configuration is desirable.
Constraints
Due to the ALU
Recall
that the ALU itself has two inputs and one output.
We
consider how to create a bus structure for the CPU that will make efficient
use of this ALU.?For this discussion, we
focus on the addition operation
associated with updating the PC (Program Counter).
One朆us
Design for the CPU
The
simplest design for the CPU calls for one common internal bus.
The
restriction that only one binary data set can be on a single bus at
any given time gives rise to severe timing problems.
Specifically,
it will take two clock pulses to put the two arguments (PC and 1)
on the bus and one clock pulse to transfer the updated value to the PC.
This
one朾us design calls for two holding registers, here called 揧?and 揨?
The control signals required for this structure are:
T1:?1 ?/span> Bus, Bus ?/span> Y.
T2:?PC ?/span> Bus, add.
T3:?Z ?/span> Bus, Bus ?/span> PC.
The
addition takes three clock pulses.
It
is easy to show that a 2朾us design requires
two clock pulses to perform the addition.
Efficient
Addition Requires a Three朆us Structure
With
this structure, the CPU can complete the addition in one clock cycle.
This
example is only one case in which the CPU design is considerably simplified
by having a three bus structure.
It can be seen that having
three internal busses only modestly increases the design
complexity of the CPU.?This is considered
a good trade杘ff.
Immediate
Implications of the Three朆us Design
The
design of the CPU calls for it to have three internal busses.
These
are called B1, B2, and B3.
B1
and B2 serve as input busses for the ALU.
B3
serves as an output bus for the ALU.
This design can be seen
in another light.
B1
and B2 are the only busses to which any register can transfer data directly.
B3
is the only bus that can transfer data directly to any register.
The protocol for
register杢o杛egister transfer becomes as follows:
1.牋牋 Transfer from the source register to either
bus B1 or bus B2 (but not both).
2.牋牋 Signal the ALU to connect the appropriate
input bus to bus B3.
3.牋牋 Transfer the contents of bus B3 to the
destination register.
This
implies two additional ALU control signals: tra1
and tra2
牋牋牋?tra1牋牋牋牋 transfer
the contents of B1 to B3
牋牋牋?tra2牋牋牋牋 transfer
the contents of B2 to B3
More
Requirements of the Common Fetch Sequence
Let抯 repeat the common fetch
sequence and examine it for more requirements.
Fetch, T0:牋牋牋 (PC) ?/span> B1, tra1,
B3 ?/span> MAR, READ.
Fetch, T1:牋牋牋 (PC) ?/span> B1, 1 ?/span> B2, add,
B3 ?/span> PC.
Fetch,
T2:牋牋牋 (MBR) ?/span> B2, tra2,
B3 ?/span> IR.
T0:?We have handled the requirements for bus
transfer.?This demands the signal
牋牋牋?tra1 to the ALU.?The READ
control signal goes to the memory interface.
T1:?We have handled these requirements completely.
T2:?Here we have two more registers to be assigned
to input busses.
牋牋牋?My earlier designs required that
the Memory Buffer Register and Instruction
牋牋牋?Register be assigned to different
busses, so this design reflects that.
Connecting
the IR to Bus B1
The
structure of the IR (Instruction Register) calls for bits to be sent directly
to the Control Unit and bits to be sent to the bus B1.
We
focus on the twenty lower order bits of the IR: IR19 ?IR0.
In
some instructions these bits IR19 ?IR0 form an address
for accessing memory.
In
some instructions these bits IR19 ?IR0 are interpreted
as an immediate operand,
牋牋牋?either a 20朾it (five hexadecimal digit) bit mask,
牋牋牋?or a 20朾it two抯朿omplement
signed integer.
In
some instructions,牋牋?bits IR19
?IR17 are part of the instruction and
牋牋牋牋牋牋牋牋牋牋牋牋牋牋牋牋牋牋牋?bits
IR16 ?IR0 are not used.
In
any case, provision is made to transfer only bits IR19 ?IR0
to bus B1.
This
transfer is enabled by the signal IR ?/span> B1.
Sign
Extension in Connecting the IR to Bus B1
Two
of the immediate instructions, LDI and ADDI, require the contents of bits IR19
?IR0 to be sign extended and treated as a 32朾it two抯朿omplement
integer.
The
other instructions that use bits IR19 ?IR0 treat them as
an unsigned integer.
To
handle this we have a control signal 揈xtend?/b>,
which is emitted by the control unit.
Here
is a representation of the transfer mechanism for the IR.
Labeling
Control Signals
Control
signals are Boolean signals with two values:
牋牋牋?Logic 1牋?Usually
asserted as + 5 volts.
牋牋牋?Logic 0牋?Usually asserted as 0 volts.
Each
control signal is labeled by the action that it enables.
牋牋牋?IR ?/span> B1牋牋牋牋 This
signal enables the transfer of IR19 ?IR0 to bus B1.
牋牋牋牋牋牋牋牋牋牋牋牋牋牋牋?It might
be called IR19? ?/span> B1
牋牋牋?Extend牋牋牋牋牋牋 When
IR ?/span> B1 is asserted, this
causes the transfer to
牋牋牋牋牋牋牋牋牋牋牋牋牋牋牋?be sign
extended.
Control
signals that enable data transfers to either bus B1 or bus B2 will take
effect by enabling a tri杝tate buffer.?
The IR is one of many possible inputs to B1.
The Complete
Connection Scheme for the Instruction Register
Here
is a schematic that shows the basic processes associated with the transfer.
The
Control Unit emits both signals (Extend and IR ?/span> B1).?Only the
latter is shown explicitly, due to a desire to keep the figure uncluttered.
The General
Purpose Registers
In
this version of the design, the CPU has eight general杙urpose registers.
牋牋牋?R0牋牋牋牋牋 This
register is read杘nly, holding the value 0.
牋牋牋?R1 ?R7牋 These seven registers are read/write and can be used for any
purpose.
牋牋牋牋牋牋牋牋牋牋牋?They are often
used as index registers.
Each
of these eight registers can output to either bus B1 or bus B2.
Bus
B3 can place data into any of the seven registers R1 ?R7, but is not connected
to R0.
The Complete
Register Set
Here
is the complete register set and bus structure for the CPU.?Note the two special purpose constant
registers +1 and ?, used by the Control Unit.
Attaching
the General Purpose Registers to the Bus Structure
There
are only three control signals emitted by the Control Unit that enable these
transfers.?These are:
牋牋牋?R ?/span> B1牋牋牋牋牋 The selected register is copied to bus B1.
牋牋牋?R ?/span> B2牋牋牋牋牋 The selected register is copied to bus B2.
牋牋牋?B3 ?/span> R牋牋牋牋牋 The contents of bus B3 are copied into the selected
register.
We
now ask how each of these registers is selected.
The
Control Unit uses three selector registers, each based on bit fields in the IR.
The generation of these selector registers will be discussed later.
牋牋牋?B1S牋牋牋牋 This
selects the register to be placed on B1 when R ?/span> B1 is asserted.
牋牋牋?B2S牋牋牋牋 This
selects the register to be placed on B2 when R ?/span> B2 is asserted.
牋牋牋?B3D牋牋牋牋 This
selects the register to copy the contents of B3
牋牋牋牋牋牋牋牋牋牋牋?when B3 ?/span> R is asserted.?
If B3D = 000, no transfer occurs.
Each
of the signals B1S and B2S is the control input to an 8杢o? multiplexer that
outputs to a bus through a tri杝tate buffer enabled by the appropriate control
signal.
The signal B3D is the 3朾it
input to an active杊igh 3杢o? decoder that is
enabled by the control signal B3 ?/span> R.
Figure:
Connecting a Single Bit to the Busses
Comments on
the Connection
Transfer to a register.
When
control signal B3 ?/span> R is asserted, the 3杢o? decoder is activated and asserts the clock
input of all flip杅lops associated with the selected register.
Each
flip杅lop associated with the selected register takes input from its bit line
on B3.
Output
0 of the decoder is not connected to any register, so that asserting
B3 ?/span> R when B3D = 000 has no
effect.
If
B3 ?/span> R is not asserted, all
decoder outputs are 0 and nothing happens.
Transfer from a register.
Note
that the selector registers B1S and B2S always have values, so that the output
of the multiplexer associated with each bus always copies some general杙urpose
register.
When
control signal R ?/span> B1 is asserted the selected register is output to bus B1.
If it is not asserted, either B1 is not active or a special purpose register is
feeding it.
When
control signal R ?/span> B2 is asserted the selected register is output to bus B2.
If it is not asserted, either B2 is not active or a special purpose register is
feeding it.
It
is expected that the two signals R ?/span> B1 and R ?/span> B2 can be asserted simultaneously.